Jump into any area of the platform. Each card opens its full page.
Unified projects, RTL, constraints, PDK corners, PPA runs, artifacts, ECOs, approvals and evidence.
Compare commit-level power, performance, area, timing, congestion and DRC against governed thresholds.
Trace an RTL change into affected timing paths, power, congestion and DRC with reviewable evidence.
Review PVT coverage, numerical deltas, failed simulations and golden-model provenance before signoff.
Capture design decisions, unresolved comments, accountable owners, artifacts and session exit gates.
Qualify versioned cells and IP by PDK, license, checksums, characterization and DRC/LVS evidence.
Run synthesis → PnR → signoff end-to-end.
OpenLane-style RTL→GDS simulation: designs, 11-stage runs, reports.
Browse the full algorithm catalog and run any one.
Head-to-head comparison of multiple algorithms.
Parameter sweeps across a design space.
Automatic parameter optimization via Bayes-opt.
Live-streaming algorithm output.
Load LEF/DEF/Verilog netlists.
Routing-congestion heatmaps.
Power-grid IR-drop analysis and hotspot finding.
Static timing analysis (STA) and slack reports.
Automatic IO-pin placement on the die boundary.
Standard-cell library browser.
2D/3D design visualization.
Usage and performance analytics.
Past algorithm runs and their results.
Benchmark scores and known results.
Chip architecture catalog.
Open your graded curriculum, evidence labs, progress, diagnostic and capstone workspace.
Browse the complete chip-design curriculum, glossary and engineering references.
Product lineup.
AI-assisted workflows and copilots.
Administrative settings.