SPECS, FORMATS AND ENGINEERING CHECKS

Reference Library

A curated starting point for authoritative documentation and fast engineering recall. Project requirements, licensed standards and foundry collateral always take precedence.

Reference discipline

Record the exact specification, PDK, library, rule-deck and tool version used by a project. A web page labeled “latest” is not a release baseline.

PRIMARY DOCUMENTATION

Authoritative starting points

Google / SkyWater Technology

SKY130 open-source PDK

Process rules, device models, primitive cells and digital libraries for education and open flows.

RISC-V International

RISC-V ratified specifications

Normative ISA and privileged-architecture specifications.

Efabless / OpenLane

OpenLane 2 reference manual

Flow, step, configuration, design-state and signoff reference.

OpenROAD Project

OpenROAD documentation

Primary documentation for the open-source RTL-to-GDSII application and flow.

RISC-V International

RISC-V Debug Specification

Standard hardware debug architecture, capabilities and implementation tradeoffs.

U.S. National Institute of Standards and Technology

NIST Platform Firmware Resiliency Guidelines

Guidance for protecting, detecting unauthorized change and recovering platform firmware.

DESIGN DATA

Formats by purpose

SystemVerilog / Verilog

RTL, testbench, assertion and netlist source

Used by: Front-end tools

SDC

Clocks, IO delays and timing exceptions

Used by: Synthesis and STA

Liberty

Cell function, timing, constraints and power

Used by: Synthesis, STA and power

LEF

Technology and cell/macro physical abstracts

Used by: Place and route

DEF

Placed and routed design exchange

Used by: Physical implementation

SPEF

Extracted resistance and capacitance

Used by: Post-route timing and power

SDF

Delay annotation for timing simulation

Used by: Gate-level simulation

GDSII / OASIS

Final hierarchical mask geometry

Used by: Physical verification and tapeout

UPF

Power domains, states, isolation and retention intent

Used by: Low-power design

SAIF / VCD

Switching activity and waveform data

Used by: Power and debug

QUICK RECALL

Useful first-order relationships

Dynamic power

P ≈ α · C · V² · f

Activity, switched capacitance, supply voltage and frequency determine first-order switching power.

RC time constant

τ = R · C

A first-order model for charge and discharge behavior.

Setup slack

Slack = required arrival − actual arrival

Negative setup slack means the data arrives too late.

Yield sensitivity

Good die cost ∝ wafer cost ÷ good die

Die area, defect density and process maturity influence economic yield.

Target impedance

Ztarget ≈ allowed ripple ÷ current step

A first-order PDN design target across frequency.

Energy efficiency

Efficiency = useful operations ÷ joules

Always state the workload, precision and boundary of measurement.

COLLECTIONS

Follow the source

Open digital implementation

Primary flow and application references for reproducible RTL-to-GDSII learning.

OpenROAD documentation OpenLane 2 reference manual SKY130 open-source PDK

Architecture specifications

Normative architecture material; always verify the version required by your project.

RISC-V ratified specifications RISC-V Debug Specification

Platform security

Primary guidance for hardware-rooted firmware protection, detection and recovery.

NIST Platform Firmware Resiliency Guidelines