Analog & Layout Engineer
Analog, custom and mixed-signal designers
Connect CMOS fundamentals, transistor sizing, robust simulation, matching layout, extraction and package effects.
Build and verify a transistor-level block through post-layout analysis.
Your curriculum
Semiconductor and CMOS Fundamentals
Build the device-level intuition needed to reason about delay, power, noise margins, process variation and physical layout.
PDKs, Standard-Cell Libraries and Design Formats
Understand the process design kit and the logical, physical, timing, parasitic and mask-data views exchanged across the flow.
Analog and Mixed-Signal IC Design
Design, simulate, lay out and verify transistor-level analog blocks and their interfaces with digital systems.
Power, IR Drop, EM, Thermal and Reliability
Analyze power consumption and ensure supply, interconnect, temperature and aging remain within lifetime limits.
Packaging, Chiplets, SI/PI and Board Integration
Co-design die, package and board connectivity for power delivery, signal integrity, thermal performance, test and manufacturability.
Physical Verification, Signoff and Tapeout
Prove geometric manufacturability, connectivity, timing, power integrity and release completeness before mask data handoff.
How to use this path
Complete each practical exercise, save evidence from the linked platform tools, and use every module’s checklist for a peer review before advancing.