Semiconductor and CMOS Fundamentals
Build the device-level intuition needed to reason about delay, power, noise margins, process variation and physical layout.
Overview
Integrated circuits are built by patterning transistors, interconnect and insulating layers on a semiconductor wafer. Digital design abstracts those devices into logic gates, but voltage, current, capacitance, resistance and manufacturing variation still determine whether a design works.
CMOS logic uses complementary pull-up and pull-down networks. Its practical behavior depends on threshold voltage, drive strength, load capacitance, transition time, temperature and supply voltage—not only Boolean truth tables.
Learning objectives
Explain MOSFET switching and CMOS logic
Relate RC delay to geometry and load
Separate dynamic, leakage and short-circuit power
Understand PVT variation and noise margins
Core concepts
MOSFET
A voltage-controlled device whose gate modulates current between source and drain.
CMOS inverter
Complementary PMOS/NMOS pair that restores logic levels and forms the basis of digital standard cells.
PVT
Process, voltage and temperature conditions used to characterize behavior across manufacturing and operation.
RC delay
Interconnect and gate delay arising from resistance charging or discharging capacitance.
Noise margin
Tolerance between guaranteed output levels and input thresholds before logic becomes ambiguous.
Power
Dynamic switching, short-circuit and leakage components; dynamic power is commonly approximated by αCV²f.
Engineering workflow
Model the device
Identify terminals, operating region and body effects.
• Device geometry
• Bias voltages
• Process model
• Current behavior
• Operating point
Build the gate
Compose pull-up and pull-down networks for the Boolean function.
• Logic function
• Transistor sizes
• Schematic
• Truth table
Characterize
Sweep input slew, output load and PVT corners.
• SPICE netlist
• Stimulus
• Corners
• Delay
• Slew
• Energy
• Noise
Layout and verify
Create geometry and verify rules, connectivity and parasitics.
• PDK rules
• Schematic
• Layout
• DRC/LVS
• Extracted netlist
Metrics and interpretation
Propagation delay
Time from an input transition to the corresponding output transition.
Energy per transition
Energy consumed for a switching event at a stated load and voltage.
Static leakage
Current consumed when logic is not switching.
Signoff checklist and pitfalls
Evidence checklist
- Valid device models and PVT corners selected
- Input slew and output load are realistic
- Noise margins remain positive
- Extracted parasitics agree with intended connectivity
Common pitfalls
•
Treating transistors as ideal switches•
Using only typical corner results•
Ignoring wire capacitance and coupling•
Confusing power with energy