Product Requirements and System Architecture
Translate a market problem into workloads, interfaces, PPA targets, safety requirements and an implementable chip architecture.
Overview
Architecture begins with measurable workloads and constraints. A useful specification connects user-visible outcomes to throughput, latency, energy, memory bandwidth, availability, cost and software compatibility.
Partitioning decides what belongs in software, programmable processors, accelerators, memories, analog blocks, package components or external devices. Early choices dominate downstream verification and physical-design cost.
Learning objectives
Write measurable chip requirements
Construct workload and bandwidth models
Partition hardware and software
Create a traceable architecture decision record
Core concepts
Workload
Representative operations, data shapes, traffic patterns and quality constraints used to size the system.
PPA
Power, performance and area—the central implementation tradeoff, usually extended with cost and risk.
Roofline model
Relates attainable performance to compute throughput and memory bandwidth.
Memory hierarchy
Registers, caches, scratchpads, on-chip SRAM, HBM/DRAM and storage organized by latency, bandwidth and capacity.
Interface contract
Protocol, timing, ordering, error and reset behavior at a block boundary.
Traceability
Link from product requirement to architecture decision, RTL, verification evidence and signoff result.
Engineering workflow
Define outcomes
Convert customer and product needs into measurable acceptance criteria.
• Use cases
• Market constraints
• Requirements
• Success metrics
Model workloads
Quantify operations, locality, bandwidth and latency.
• Traces
• Algorithms
• Performance model
• Traffic model
Explore architecture
Compare partitioning, topology, memory and compute alternatives.
• Models
• Technology assumptions
• Trade study
• PPA envelope
Baseline contracts
Freeze interfaces, budgets and verification intent with change control.
• Chosen architecture
• Architecture spec
• Block budgets
• Decision records
Metrics and interpretation
Throughput
Completed work per unit time under a stated workload.
Tail latency
High-percentile response time, often more important than the average.
Energy efficiency
Useful operations per joule under a reproducible workload.
Bandwidth utilization
Sustained data rate relative to available interface capacity.
Signoff checklist and pitfalls
Evidence checklist
- Every requirement has an owner and verification method
- Workloads include typical and worst cases
- Block PPA budgets reconcile to the chip budget
- Reset, clock, power and security architectures are documented
- Major assumptions have sensitivity analysis
Common pitfalls
•
Optimizing a benchmark instead of the product workload•
Ignoring data movement energy•
Under-specifying error behavior•
Freezing interfaces before traffic analysis