Clock, Reset and CDC/RDC Design
Design reliable clock and reset domains, crossing protocols, synchronizers, constraints and structural verification.
Overview
Clock-domain crossings can violate setup and hold requirements independent of nominal frequency. Correct solutions depend on data semantics: single-bit level, pulse, multi-bit data, event count or asynchronous stream.
Reset-domain crossings have similar hazards during assertion or release. Structural analysis must be paired with protocol reasoning and timing constraints; a synchronizer alone does not guarantee coherent data transfer.
Learning objectives
Classify crossing types
Choose synchronizer, handshake or asynchronous FIFO
Constrain CDC paths correctly
Review reset sequencing and reconvergence
Core concepts
Metastability
A state element temporarily fails to resolve to a valid logic level after a timing violation.
MTBF
Statistical mean time between synchronizer failures, driven by event rate, clock rate and resolution time.
Reconvergence
Separately synchronized signals meet again and may represent different source cycles.
Async FIFO
Dual-clock storage with safely synchronized Gray-coded pointers.
RDC
Reset-domain crossing analysis for signals whose reset behavior differs.
Generated clock
Clock derived from another clock with a defined waveform and relationship.
Engineering workflow
Inventory domains
Identify clocks, resets, derivations and operating modes.
• RTL
• Clock plan
• Domain map
Classify crossings
Determine semantics, rate and coherency requirements.
• Connectivity
• Protocol intent
• Crossing classification
Implement structures
Apply synchronizers, handshakes, FIFOs or bundled-data protocols.
• Classification
• CDC-safe RTL
Verify and constrain
Run structural, assertion and timing checks.
• RTL
• SDC
• CDC/RDC report
• Reviewed waivers
Metrics and interpretation
Unwaived violations
Structural crossings without an approved implementation and rationale.
Synchronizer MTBF
Estimated reliability for a stated process, voltage, temperature and activity.
Reconvergence count
Crossing paths whose independently synchronized values reconverge.
Signoff checklist and pitfalls
Evidence checklist
- All clocks and resets declared
- Crossings classified by semantics
- Synchronizer cells protected from optimization
- Reconvergence and pulse-width risks reviewed
- Constraints do not hide functional CDC defects
Common pitfalls
•
Synchronizing each bit of a bus independently•
Missing short pulses•
Treating false paths as CDC fixes•
Asynchronous reset release without synchronization