Logic Synthesis and Design for Test
Map RTL into a technology library while preserving intent, meeting constraints and preparing controllable, observable silicon test structures.
Overview
Synthesis elaborates RTL, optimizes Boolean and sequential logic, and maps it to characterized library cells under timing, area, power and design-rule constraints.
DFT adds structures such as scan chains, test points, memory BIST and boundary scan so manufacturing defects can be detected efficiently. Test intent must be integrated before physical design.
Learning objectives
Read synthesis reports and mapped netlists
Write realistic synthesis constraints
Understand scan, ATPG, MBIST and JTAG
Separate functional and test modes safely
Core concepts
Elaboration
Resolve parameters, hierarchy and language constructs into a design model.
Technology mapping
Cover optimized logic with cells from a target library.
Equivalence checking
Prove that transformed implementation preserves the intended function.
Scan chain
Shift path connecting state elements for controllability and observability.
ATPG
Automatic generation of patterns targeting modeled manufacturing faults.
Fault coverage
Detected target faults divided by detectable target faults under the selected model.
Engineering workflow
Elaborate and constrain
Resolve design, clocks, modes, IO and exceptions.
• RTL
• Libraries
• SDC
• Elaborated design
Optimize and map
Transform logic to meet cost and design rules.
• Design
• Constraints
• Mapped netlist
• QoR reports
Insert test structures
Add scan, compression, test points and memory test logic.
• Netlist
• Test specification
• DFT netlist
• Scan protocol
Verify and hand off
Run equivalence, DFT rules, ATPG and timing checks.
• Pre/post netlists
• Coverage
• Constraints
• Physical handoff
Metrics and interpretation
Cell area
Sum of mapped cell areas before physical utilization overhead.
Worst slack
Most negative setup or hold timing margin in the synthesis view.
Fault coverage
Effectiveness of generated patterns for a defined fault model.
Test data volume
Bits and cycles required to apply manufacturing test.
Signoff checklist and pitfalls
Evidence checklist
- No unresolved or black-box logic
- Timing constraints cover all modes
- Equivalence passes after major transformations
- DFT rule violations resolved
- Test clocks, resets and power modes are physically feasible
Common pitfalls
•
Using ideal clocks and IO delays•
Ignoring high-fanout control nets•
Late scan insertion disrupting floorplan•
Reporting coverage without excluded fault rationale