Constraints, Static Timing and MMMC Analysis
Model clocks, data paths, exceptions, variation and multiple operating scenarios to prove setup and hold timing.
Overview
Static timing analysis propagates arrival times and required times through a timing graph without enumerating input vectors. Its result is only as valid as clocks, IO assumptions, libraries, parasitics, uncertainty and exceptions.
Multi-mode multi-corner analysis covers functional and test modes across process, voltage, temperature and RC conditions. Setup and hold often have different worst cases; variation and signal integrity change path delay and uncertainty.
Learning objectives
Write and audit SDC constraints
Interpret setup, hold, recovery and removal
Build MMMC scenarios
Debug path groups and timing exceptions
Core concepts
Arrival time
Time at which a signal transition reaches a timing point.
Required time
Latest or earliest acceptable arrival time at a timing point.
Slack
Required time minus arrival time for setup-style checks; positive means margin.
OCV
On-chip variation modeling for correlated and uncorrelated delay differences.
False path
A path that is functionally impossible or intentionally excluded from a timing check.
Multicycle path
A functional path allowed more than one destination-clock period, with setup and hold implications.
Engineering workflow
Create clocks and IO model
Define waveforms, relationships, latency, uncertainty and external delays.
• Clock architecture
• Interface budgets
• Base SDC
Build scenarios
Associate modes, libraries, RC corners, voltage and temperature.
• PDK data
• Operating modes
• MMMC configuration
Analyze paths
Report setup, hold, clock gating and asynchronous checks.
• Netlist/layout
• Parasitics
• Path reports
• Coverage report
Close and audit
Fix design or constraints; review exceptions and unconstrained endpoints.
• Violations
• Timing-clean scenarios
• Exception evidence
Metrics and interpretation
WNS
Worst negative slack, indicating the single most severe violation.
TNS
Sum of negative slack across violating endpoints.
Unconstrained endpoints
Sequential or output endpoints without a meaningful timing requirement.
Path coverage
Percentage of relevant startpoint-endpoint relationships analyzed.
Signoff checklist and pitfalls
Evidence checklist
- All clocks and generated clocks are defined
- No unintended unconstrained endpoints
- Exceptions are justified by function and reviewed
- Setup and hold close across required scenarios
- Parasitics, libraries and variation models match the signoff intent
Common pitfalls
•
Fixing timing by adding unsafe false paths•
Forgetting hold impact of multicycle setup•
Using pre-route wire estimates at signoff•
Ignoring recovery, removal and clock-gating checks