Fabrication, Yield and Manufacturing Test
Understand wafer fabrication, process control, defect/yield economics, production test, characterization and quality feedback.
Overview
Fabrication repeatedly deposits, patterns, etches, implants and planarizes materials to create devices and interconnect. Design rules and process models encode the foundry interface, but manufacturing variation and defects remain statistical.
Production test screens wafers and packaged parts, assigns bins, measures parametric limits and supports diagnosis. Yield learning connects layout, process, design margin and test data to improve quality and cost.
Learning objectives
Describe major fabrication steps
Model defect-limited and parametric yield
Understand wafer sort and final test
Use test and diagnosis data for yield learning
Core concepts
Lithography
Pattern transfer using light-sensitive material and masks.
FEOL/BEOL
Front-end device formation and back-end interconnect formation.
Defect density
Statistical density of yield-impacting defects per unit area.
Wafer sort
Electrical probing and classification before dicing and packaging.
Shmoo plot
Pass/fail map over operating parameters such as voltage and frequency.
Diagnosis
Inference from failing responses to likely defect locations or mechanisms.
Engineering workflow
Fabricate wafers
Execute controlled process steps and monitor inline structures.
• Mask set
• Process recipe
• Processed wafers
• Inline data
Wafer sort
Apply structural, functional and parametric tests.
• Patterns
• Probe program
• Die bins
• Wafer maps
Assemble and final-test
Package good candidates and screen system-level behavior.
• Good die
• Package
• Qualified units
Learn and improve
Correlate spatial, diagnosis, process and design data.
• Test history
• Process data
• Yield actions
• Limit updates
Metrics and interpretation
Yield
Good units divided by total units at a defined manufacturing stage.
DPPM
Defective parts per million shipped or projected.
Test time
Tester seconds per unit, a direct production-cost driver.
Guardband
Margin between test limits and required operation to protect outgoing quality.
Signoff checklist and pitfalls
Evidence checklist
- Test coverage supports product quality goal
- Limits are correlated to specification and measurement capability
- Wafer maps and diagnosis preserve traceability
- Burn-in and screening have evidence-based purpose
- Yield monitoring distinguishes process, design and test effects
Common pitfalls
•
Equating high fault coverage with low DPPM•
Over-screening with excessive guardband•
Discarding spatial wafer context•
Treating tester correlation as a one-time task