ISA, Microarchitecture and Datapath Design
Move from architectural behavior to pipelines, execution units, control, hazards, caches and measurable performance.
Overview
An instruction-set architecture defines software-visible behavior. Microarchitecture defines how a particular implementation realizes that behavior using pipelines, queues, execution units, prediction, caches and interconnect.
Correctness requires precise treatment of ordering, exceptions, privilege, interrupts, reset and coherency. Performance requires a model that accounts for instruction mix, dependencies, cache behavior, contention and recovery penalties.
Learning objectives
Separate ISA from implementation
Design pipelines and hazard handling
Model CPI and memory effects
Specify exceptions, privilege and observability
Core concepts
ISA
Software-visible instructions, registers, memory model, exceptions and privilege behavior.
Pipeline
Overlapped execution stages separated by state elements.
Hazard
Data, control or structural condition that prevents the next operation from proceeding safely.
CPI
Cycles per instruction; decomposed into ideal issue cost plus stalls and recovery penalties.
Coherency
Rules ensuring observers see compatible values when data is cached in multiple places.
Precise exception
Architectural state appears as if all earlier operations completed and no later operation did.
Engineering workflow
Select architectural contract
Choose ISA, privilege, memory model and extensions.
• Software needs
• Workloads
• ISA profile
• Compliance targets
Partition datapath and control
Define stages, resources, queues and state.
• ISA
• Frequency target
• Block diagram
• Pipeline table
Model performance
Estimate throughput and sensitivity to stalls, misses and contention.
• Traces
• Latency assumptions
• CPI model
• Bottleneck analysis
Specify corner behavior
Document reset, exceptions, flushes, privilege and debug.
• Architecture
• State-transition rules
• Verification plan
Metrics and interpretation
IPC/CPI
Retired instructions per cycle or its inverse.
Mispredict penalty
Lost cycles after incorrect control speculation.
Cache MPKI
Cache misses per thousand instructions.
Occupancy
Average utilization of queues, buffers or execution resources.
Signoff checklist and pitfalls
Evidence checklist
- ISA compliance target is versioned
- All hazards have detection and recovery behavior
- Exceptions and interrupts are precise
- Performance model matches representative traces
- Debug and performance counters are specified
Common pitfalls
•
Ignoring backpressure and queue fullness•
Validating only straight-line instruction streams•
Conflating simulator assumptions with RTL behavior•
Leaving privilege and reset late