Memory Subsystems and IP Integration
Select, configure and integrate SRAM, caches, ROM, nonvolatile memory and third-party IP with correct interfaces, test and physical views.
Overview
Memory dominates area, power and performance in many chips. Architecture choices include banking, ports, word width, depth, ECC, replacement, coherence and traffic scheduling.
Hard and soft IP integration requires a complete view set: logical models, timing and power libraries, physical abstracts, layout, verification models, constraints, test protocols, software collateral and licensing provenance.
Learning objectives
Size memory hierarchy from workload
Choose banking, ports and ECC
Integrate hard macros and abstract views
Verify test, reset, power and coherency behavior
Core concepts
Banking
Partitioning storage for parallel access, power control or physical distribution.
ECC
Redundant coding used to detect and correct stored-data errors.
Macro abstract
LEF or equivalent physical view containing boundary, pins and obstructions.
Liberty model
Characterized timing, power and functional behavior used by implementation tools.
Coherence
Rules that maintain compatible memory values across caches and agents.
BIST
On-chip controller and algorithms used to test memory arrays.
Engineering workflow
Model traffic
Quantify capacity, bandwidth, locality, concurrency and QoS.
• Workloads
• Memory requirements
Choose organization
Select hierarchy, banks, ports, ECC and policies.
• Requirements
• Memory architecture
Integrate views
Verify logical, timing, power, physical and test collateral.
• IP release
• Qualified IP package
Verify system behavior
Test ordering, errors, reset, test and low-power operation.
• Integrated design
• Coverage
• Performance evidence
Metrics and interpretation
Hit rate
Fraction of accesses satisfied at a hierarchy level.
Effective bandwidth
Useful payload rate after protocol and contention overhead.
Access energy
Energy per read/write for a stated configuration and corner.
Correctable error rate
Observed or projected errors handled by the selected ECC.
Signoff checklist and pitfalls
Evidence checklist
- All required IP views share a release/version
- Memory traffic meets latency and bandwidth goals
- ECC and error reporting are verified
- MBIST and repair interfaces are integrated
- Macro placement, pin access and power intent are feasible
Common pitfalls
•
Sizing capacity without bandwidth analysis•
Mixing collateral from different macro releases•
Ignoring simultaneous-access conflicts•
Late discovery of macro test and repair pins