DFT & Product Engineer
Test, yield and product engineers
Connect scan and memory test to production screening, diagnosis, yield learning and silicon characterization.
Design a test strategy that supports coverage, cost, quality and actionable diagnosis.
Your curriculum
Logic Synthesis and Design for Test
Map RTL into a technology library while preserving intent, meeting constraints and preparing controllable, observable silicon test structures.
Memory Subsystems and IP Integration
Select, configure and integrate SRAM, caches, ROM, nonvolatile memory and third-party IP with correct interfaces, test and physical views.
Fabrication, Yield and Manufacturing Test
Understand wafer fabrication, process control, defect/yield economics, production test, characterization and quality feedback.
Post-Silicon Bring-up, Validation and Debug
Bring first silicon to life, characterize margins, diagnose failures and connect laboratory evidence back to design assumptions.
EDA Automation, AI and Engineering Governance
Build reproducible flows, use optimization and AI responsibly, track PPA regressions and retain evidence for human decisions.
How to use this path
Complete each practical exercise, save evidence from the linked platform tools, and use every module’s checklist for a peer review before advancing.